One of the most popular Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technologies available today is the complementary MOS (metal oxide semiconductor), or CMOS, technology. This technology makes use of both P and N channel devices in the same substrate material. Such devices are extremely useful, since the same signal that turns on a transistor of one type is used to turn off a transistor of the other type. A MOSFET transistor consists of three regions, referred to as the “source”, the “gate” and the “drain”. In an N-type transistor, the source and drain regions are doped with N type material and the substrate doped with P type material. In a P-type transistor, the source and drain regions are doped with P type material, and the substrate is doped with N type material. The source and drain regions are quite similar, and are labeled depending on to what they are connected. The source is the terminal, or node, which acts as the source of charge carriers; charge carriers leave the source and travel to the drain. In the case of an N channel, of N-type, MOSFET, the source is the more negative of the terminals; in the case of a P channel device, it is the more positive of the terminals. CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications and signal processing equipment.
Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in the battery life in the case of battery-powered applications and affects reliability, packaging and cooling costs. The main sources of power dissipation are: (i) capacitive power dissipation due to the charging and discharging of the load capacitance (ii) short circuit currents due to the existence of a conducting path between the voltage supply and ground for the brief period during which a logic gate makes a transition and (iii) leakage current.
Leakage current in CMOS circuits is defined as the drain current when the gate-source voltage is zero. Leakage current consists of two main sources, reverse bias diode currents, which are due to stored charge between the drain and bulk of active transistors and sub-threshold currents, which are due to carrier diffusion between the source and drain of the off transistors. Of these two sources of leakage current, the sub-threshold current is the major component of leakage current and therefore of greatest concern.
There are techniques known in the art to reduce the power dissipation in CMOS circuits. It is known in the art that the short circuit power dissipation can be reduced to 10% of total power dissipation by designing the circuit to have equal input and output rise/fall edge times. The power dissipation resulting from switching activity is the dominant component for technology processes having feature size larger than 1 μm. With technology processes maturing towards deep submicron regime, the feature size of the transistors are being reduced, thereby reducing the load capacitances. The reduction in feature size also forces a reduction in the supply voltage because the reduced feature size cannot withstand the high supply voltages, thereby forcing supply voltage scaling. The quadratic dependence of switching power on supply voltage is taken benefit of by voltage scaling techniques for dynamic power savings. However, this technique also drastically increases the delay as the supply voltage approaches the threshold voltage (Vt) of the devices. In order to facilitate voltage scaling without affecting the performance, the threshold voltage must also be reduced. In general, the ratio between the supply voltage and the threshold voltage should be at least five so that the performance of the CMOS circuits is not affected. This ratio also leads to better noise margins and helps to avoid the hot-carrier effects in short channel devices.
Scaling down of the threshold voltage (Vt) results in an exponential increase of the sub-threshold leakage current. It can be seen from FIG. 1 that the leakage power is only 0.01% of the active power for 1 μm technology, while it is 10% of the active power for 0.1 μm technology. As such, there is a five-fold increase in leakage power as the technology process advances to a new generation of deep submicron and nanometer circuits. Projecting these trends, it can be seen that the leakage power dissipation will equal active power dissipation within a few generations. Hence, efficient leakage power reduction methods are very critical for the deep submicron and nanometer circuits.
Numerous methods for leakage power control have been reported in the literature. Known work in the art makes use of the dependence of the leakage current on the input vector to the gate of the transistor. With additional control logic, the circuit is put into a low-leakage standby state when it is idle and restored to the original state when reactivated. The use of a reactivation state forces the need to remember the original state information before going to low-leakage standby state. This requires special latches, thereby increasing the area of the circuit by about five times, in the worst-case. Additionally, the amount of time for which the unit remains in idle state should be long enough so that the dynamic power consumed in forcing the circuit to a low-leakage state and the leakage power dissipated in the standby state together is less than the leakage power without the technique.
Another technique for leakage power control known in the art is referred to as power gating. Power gating turns off the devices by cutting off their supply voltage. This technique makes use of a bulky NMOS and/or PMOS device (sleep transistor) in the path between the supply voltage and ground. The sleep transistor is turned on when the circuit is active and turned off when the circuit is in an idle state with the help of a sleep signal, thereby creating virtual power and ground rails in the circuit. Hence, there is a significant detrimental effect on the switching speed when the circuit is active. The identification of the idle regions of the circuit and the generation of the sleep signal require additional hardware capable of predicting the circuit states accurately. This additional hardware consumes power throughout the circuit operation even when the circuit is in an idle state to continuously monitor the circuit state and control the sleep transistors.
The use of multiple threshold voltage CMOS (MTCMOS) technology for leakage control is also known in the art. With this method, the transistors of the gates are at a low threshold voltage and the ground is connected to the gate through a high threshold voltage NMOS gating transistor. The logical function of a gating transistor is similar to that of a sleep transistor. With this method, the existence of reverse conduction paths tends to reduce the noise margin or in the worst case may result in complete failure of the gate. Moreover, there is a performance penalty since high threshold transistors appear in series with all the switching current paths. A variation of the MTCMOS technique is the Dual Vt technique, which uses transistors with two different threshold voltages. Low threshold transistors are used for the gates on the critical path and high threshold transistors are used for those not in the critical path. In both MTCMOS and Dual Vt methods, additional mask layers for each value of threshold voltage are required for fabricating the transistors selectively according to their assigned threshold voltage values. The use of additional mask layers makes the fabrication process increasingly complex.
In addition to these limitations, the techniques discussed above suffer from “turning on latency”, that is, when the idle subsections of the circuit are reactivated, they cannot be used immediately because some time is needed before the sub-circuit returns to its normal operating condition. The latency for power gating is typically a few cycles, and for Dual Vt technology, can be much longer. Also, the techniques known in the art are not effective in controlling the leakage power when the circuit is in active state.
It is additionally known in the art to use the concept of forced stacks for leakage control. Forced stacking introduces an additional transistor for every input of the gate in both N- and P-networks. This ensures that two transistors are Off instead of one for every Off-input of the gate and hence, makes a significant savings on the leakage current. However, the loading requirements for each input introduced by the forced stacking, reduces the drive current of the gate significantly. This results in a detrimental impact on the speed of the circuit.
In one prior art method, a combination of sleep transistors and the stacking effects are used to reduce leakage power. This method identifies a circuit input vector for which the leakage current of the circuit is the lowest possible. The sleep signal controlled transistors are inserted away from the critical path where only one transistor is Off when low leakage input vector is applied to the circuit. Hence, this technique is input vector dependent. Moreover, as this technique uses sleep transistors, it requires additional hardware to control the sleep transistors. The additional hardware consumes power in both idle and active states of the circuit.
Accordingly, what is needed in the art is an efficient leakage power reduction method for deep submicron and nanometer circuits that is input vector independent, minimizes the additional hardware required, is effective in both idle and active states, has a minimal impact on switching speed of the circuit and does not add additional fabrication complexity to the circuit.